Adaptec AIC-6915 Informacje Techniczne Strona 95
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7-23
Register Descriptions
PMCSR (Power Management Control/Status) Register
Type: R/W
Internal Registers Su/jointfilesconvert/419897/bgroup: PCI Functional Registers
Byte Address: 54h - 57h
18:16 r 1h
PMVersion
: This field indicates that there are 4 bytes of General
Purpose Power Management registers implemented as described in
revision 1.0 of the ‘PCI Bus Power Management Interface
Specification’.
15:8 r 00h
NextItemPtr:
This field provides an offset into the function’s PCI
configuration space pointing to the location of next item in the
function’s capability list. The AIC-6915 does not implement more
items in the list.
7:0 r 01h
PowerManagementId
: This ID indicates the start of the Power
Management Register Block
Table 7-32. Power Management Control Status Register
Bit(s) rw
Reset
Value Description/Function
31:29 r 0
PMData:
This function is not implemented. The AIC-6915 does not
provide information about the power it consumes.
23:16 r 0
Reserved:
Always read as 0.
15 r/w 0
PmeStatus:
This bit is set when the function would normally assert
the
PME_
signal independent of the state of the
P
ME
E
N
bit. Setting
this bit clears it and causes the function to stop asserting a
PME_
.
Clearing the bit has no effect.
14:13 r 0
DataScale:
This function is not implemented. The AIC-6915 does
not provide information about the power it consumes.
12:9 r 0
DataSelect:
This function is not implemented. The AIC-6915 does
not provide information about the power it consumes.
8r/w 0
PmeEn:
This bit enables the function to assert
PME_
. If this bit is
cleared assertion of
PME_
is disabled.
7:2 r 0
Reserved:
Always read as 0.
1:0 r/w
PowerState
: This 2-bit field determines the power state of the
AIC-6915
‘
00
’ - D0
‘
01
’ - D1
‘
10
’ - D2
‘
11
’ - D3
Reset Value:
In CardBus mode, (when the EPROM A0 pin is
sampled low at reset), the PowerState starts at D3. Otherwise, it
starts at D0.
Table 7-31. Power Management Register (Continued)
Bit(s) rw
Reset
Value Description/Function
- AIC-6915 1
- © 1998, Adaptec, Inc 2
- Electronic Support 4
- Technical and Product Support 4
- Contents 5
- 4 PCI Module Architecture 6
- 7 Register Descriptions 7
- 8 Sample Driver 7
- ▼ ▼ ▼ ▼ 11
- Introduction 15
- Ethernet 16
- Internal Buffer Management 17
- 32/64-bit PCI 17
- Block Diagram 19
- Receive Architecture 21
- Producer and Consumer Indices 22
- Receive DMA Descriptor Queues 22
- Normal Mode 23
- Polling Mode 23
- 32-bit Addressing Mode 24
- 64-bit Addressing Mode 24
- Accepting frames 25
- Start Index 26
- Transmit Architecture 31
- CALTCP bit to zero in the 32
- Transmit Data Structure 34
- Transmit Register Set 35
- PCI Module Architecture 43
- PCI Block Diagram 45
- PCI Master Module 46
- 64-bit PCI Bus Master 47
- Arbitration 48
- Power Management 50
- Retry Function 51
- Response to PCI Commands 51
- Configuration Address Space 53
- Expansion ROM Address Space 54
- Memory Address Space 54
- Illegal Behavior 56
- Frame Processor Architecture 57
- Wake-up Mode 58
- Transmit Checksum Accelerator 58
- GFP Address Space 59
- External Registers 60
- Instruction Formats 62
- AIC-6915 Internal Registers 67
- AIC-6915 Address Space 74
- AIC-6915 PCI Address Map 74
- Terminology 76
- PCI Registers 77
- Byte Address: 04h - 05h 78
- 2:0 r 0 AddressSpaceIndicator 84
- Byte Address: 34h 86
- Byte Address: 3Ch 86
- Byte Address: 3Fh 88
- Byte Address: 40h - 43h 89
- Byte Address: 54h - 57h 95
- Ethernet Registers 99
- Type: R/W 100
- Byte Address: 74h - 77h 100
- Register Descriptions 101
- Transmit Registers 109
- OMPLETION 115
- Byte Address: BCh - BFh 116
- Byte Address: C0h - C3h 117
- Receive Registers 120
- Byte Address: F8h- FBh 130
- PCI Diagnostic Registers 131
- Byte Address: 0104h - 0107h 132
- Byte Address: 011Ch - 011Fh 136
- PCI CardBus Registers 138
- Byte Address: 013Ch - 013Fh 140
- Additional Ethernet Registers 141
- MAC Control Registers 143
- Byte Address: 5004h- 5007h 145
- Byte Address: 5070h - 5073h 152
- Address Filtering Registers 154
- MAC Statistic Registers 156
- Sample Driver 161
- // configuration space 163
- Receive Process 167
- Type 2 Completion Descriptor 168
- Type 3 Completion Descriptor 168
- 32-bit buffer descriptor 168
- 64-bit buffer descriptor 168
- Two Receive Queues 169
- Receive Polling Model 169
- Receive Initialization 169
- Receive Interrupt Handling 175
- Transmit Process 176
- Type 0 descriptor 178
- Type 1 descriptor 178
- Two Transmit Queues 180
- Transmit Initialization 181
- Transmit Handling 185
- AIC-6915 DDK Features 189
- DDK Development Environment 190
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