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AIC-6915 Ethernet LAN Controller Programmer’s Manual
RxCompletionQueue1Ctrl
Type: R/W
Internal Registers Su/jointfilesconvert/419897/bgroup: Ethernet Functional Registers
Byte Address: BCh - BFh
4r/w0
CommonQueueMode:
When this bit is set, the receive completion
queues are disabled and all completion descriptors and general chip
status are DMA-transferred to the Transmit Completion Queue. This
bit overrides any values specified for the receive completion queues.
In this mode the maximum receive completion size is 8-bytes.
3:0 r/w 0
TxCompletionQueueThreshold
specifies a threshold equals to
4*T
X
C
OMPLETION
Q
UEUE
T
HRESHOLD
.
If
T
X
C
OMPLETION
T
HRESHOLD
M
ODE
is ‘0’ and the number of
empty
entries in transmit queue is less or equal to the threshold, an
interrupt status bit is set.
If
T
X
C
OMPLETION
T
HRESHOLD
M
ODE
is ‘1’ and the number of
valid
completion entries in transmit queue is greater than or equal to the
threshold, an interrupt status bit is set.
Table 7-57. RxCompletionQueue1Ctrl Register
Bit(s) rw
Reset
Value Description/Function
31:8 r/w x
RxCompletionQ1BaseAddress[31:8]:
This field contains the
starting address of the queue in host memory. It is written by the
host driver during initialization and read by the AIC-6915. The
amount of host memory allocated for the completion queue is either
4-KBytes, 8-KBytes, or 16-KBytes (programmable by bits 5:4,
R
X
C
OMPLETION
Q2T
YPE
). The starting address must be aligned to a
256-byte boundary.
7r/w0
RxCompletionQ1_64bitAddress:
The bit indicates if Receive
Completion Queue 1 is located in 64-bit address space. If so, the
AIC-6915 PCI master must use 64-bit addressing mode to access the
queue.
6r/w0
RxCompletionQ1ProducerWe:
When this bit is set, the software
driver is able to write the receive completion queue producer index.
Otherwise, writes to the index are disabled.
5:4 r/w 0
RxCompletionQ1Type[1:0]:
Controls the type of the completion
descriptor.
‘
00
’ - One word completion entry.
‘01’
- Two word completion entry. The second word contains
extended status and the VLAN ID and priority.
‘10’
- Two word completion entry. The second word contains a
partial checksum and 16 status bits.
‘11’
- Four word completion entry. The entry contains a
timestamp, full status, VLAN ID and priority, and the partial
checksum.
Table 7-56. TxCompletionQueueCtrl Register (Continued)
Bit(s) rw
Reset
Value Description/Function
- AIC-6915 1
- © 1998, Adaptec, Inc 2
- Electronic Support 4
- Technical and Product Support 4
- Contents 5
- 4 PCI Module Architecture 6
- 7 Register Descriptions 7
- 8 Sample Driver 7
- ▼ ▼ ▼ ▼ 11
- Introduction 15
- Ethernet 16
- Internal Buffer Management 17
- 32/64-bit PCI 17
- Block Diagram 19
- Receive Architecture 21
- Producer and Consumer Indices 22
- Receive DMA Descriptor Queues 22
- Normal Mode 23
- Polling Mode 23
- 32-bit Addressing Mode 24
- 64-bit Addressing Mode 24
- Accepting frames 25
- Start Index 26
- Transmit Architecture 31
- CALTCP bit to zero in the 32
- Transmit Data Structure 34
- Transmit Register Set 35
- PCI Module Architecture 43
- PCI Block Diagram 45
- PCI Master Module 46
- 64-bit PCI Bus Master 47
- Arbitration 48
- Power Management 50
- Retry Function 51
- Response to PCI Commands 51
- Configuration Address Space 53
- Expansion ROM Address Space 54
- Memory Address Space 54
- Illegal Behavior 56
- Frame Processor Architecture 57
- Wake-up Mode 58
- Transmit Checksum Accelerator 58
- GFP Address Space 59
- External Registers 60
- Instruction Formats 62
- AIC-6915 Internal Registers 67
- AIC-6915 Address Space 74
- AIC-6915 PCI Address Map 74
- Terminology 76
- PCI Registers 77
- Byte Address: 04h - 05h 78
- 2:0 r 0 AddressSpaceIndicator 84
- Byte Address: 34h 86
- Byte Address: 3Ch 86
- Byte Address: 3Fh 88
- Byte Address: 40h - 43h 89
- Byte Address: 54h - 57h 95
- Ethernet Registers 99
- Type: R/W 100
- Byte Address: 74h - 77h 100
- Register Descriptions 101
- Transmit Registers 109
- OMPLETION 115
- Byte Address: BCh - BFh 116
- Byte Address: C0h - C3h 117
- Receive Registers 120
- Byte Address: F8h- FBh 130
- PCI Diagnostic Registers 131
- Byte Address: 0104h - 0107h 132
- Byte Address: 011Ch - 011Fh 136
- PCI CardBus Registers 138
- Byte Address: 013Ch - 013Fh 140
- Additional Ethernet Registers 141
- MAC Control Registers 143
- Byte Address: 5004h- 5007h 145
- Byte Address: 5070h - 5073h 152
- Address Filtering Registers 154
- MAC Statistic Registers 156
- Sample Driver 161
- // configuration space 163
- Receive Process 167
- Type 2 Completion Descriptor 168
- Type 3 Completion Descriptor 168
- 32-bit buffer descriptor 168
- 64-bit buffer descriptor 168
- Two Receive Queues 169
- Receive Polling Model 169
- Receive Initialization 169
- Receive Interrupt Handling 175
- Transmit Process 176
- Type 0 descriptor 178
- Type 1 descriptor 178
- Two Transmit Queues 180
- Transmit Initialization 181
- Transmit Handling 185
- AIC-6915 DDK Features 189
- DDK Development Environment 190
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